Career Profile
I'm a senior engineer at Qualcomm. I received a Ph.D. degree in ABKGroup from UC San Diego, one of the most famous research groups in VLSI/CAD. I specialize in programming solving an optimization problem based on C/C++/Python/Tcl.My passion for programming was fostered by physical design projects. I was the main developer of OpenROAD which is supported by Google and POSH projects from DARPA. OpenROAD was aimed at building the open-source physical design flows and I was the main developer in Task 8 (Floorplan) and Task 9 (Placement). I developed, rewrote, and maintained three projects; TritonMP, RePlAce, and OpenDP (all tools are available as 'macro_placement', 'global_placement', and 'legalize_placement' Tcl commands). My contributed tools are widely used in OpenROAD. Nowadays, OpenROAD has generated 600+ IC tapeouts successfully.
Experiences
Advanced Leakage Optimization (AdvLeakOpt): Reduced days of leakage recovery runtime (30-50%) within PT-DMSA, by utilizing the fastest C++ implementation.
Dissertation: Physical Design Methods and Research Infrastructure for Advanced VLSI Technologies
Dissertation: Clip-Shifting-Aware Lithography Pattern Classification [c1]
Papers
Conference
[c1]
M. Woo, S. Kim and S. Kang,
"GRASP based Metaheuristics for Layout Pattern Classification",
Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, pp. 512-518.
(Link)
[c2]
S. Do, M. Woo and S. Kang,
"Fence Region-Aware Multi-Deck Standard Cell Legalization",
Proc. ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), 2019, pp. 259-262.
(Link)
[c3]
T. Ajayi, D. Blaauw, T.-B. Chan, C.-K. Cheng, V. A. Chhabria, D. K. Choo, M. Coltella, R. Dreslinski, M. Fogaça, S. Hashemi, A. Hosny, A. B. Kahng, M. Kim, J. Li, Z. Liang, U. Mallappa, P. Penzes, G. Pradipta, S. Reda, A. Rovinski, K. Samadi, S. S. Sapatnekar, L. Saul, C. Sechen, V. Srinivas, w. Swartz, D. Sylvester, D. Urquhart, L. Wang, M. Woo and B. Xu,
"OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain",
Proc. Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2019, pp. 1105-1110.
(Link)
[c4]
T. Ajayi, V. A. Chhabria, M. Fogaça, S. Hashemi, A. Hosny, A. B. Kahng, M. Kim, J. Lee, U. Mallappa, M. Neseem, G. Pradipta, S. Reda, M. Saligane, S. S. Sapatnekar, C. Sechen, M. Shalan, W. Swartz, L. Wang, Z. Wang, M. Woo and B. Xu,
"Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project",
Proc. ACM/IEEE Design Automation Conference (DAC), 2019, pp. 76:1-76:4 (Invited).
(Link)
[c5]
J. Chen, I. H.-R. Jiang, J. Jung, A. B. Kahng, V. N. Kravets, Y.-L. Li, S.-T. Lin and M. Woo,
"DATC RDF-2019: Towards a Complete Academic Reference Design Flow",
Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019, pp. 1-6 (Invited).
(Link)
[c6]
V. Bandeira, M. Fogaça, J. Li, E.-M. Monteiro, I. Oliveira, R. Reis and M. Woo,
"An open road knows no borders: The contributions of UFRGS-UCSD partnership to the OpenROAD project.",
Workshop on Open-Source EDA Technology (WOSET), 2019.
(Link)
[c7]
Y. Kang, Y. Park, S. Kim, E. Kwon, T. Lim, S. Oh, M. Woo and S. Kang,
"Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling",
Proc. tomation and Test in Europe (DATE), 2020, pp. 1091-1096.
(Link)
[c8]
V. Bandeira, M. Fogaça, E.-M. Monteiro, I. Oliveira, M. Woo and R. Reis,
"Fast and Scalable I/O Pin Assignment With Divide-and-Conquer and Hungarian Matching",
Proc. IEEE International New Circuits and Systems Conference (NEWCAS), 2020, pp. 74-77.
(Link)
[c9]
J. Chen, I. H.-R. Jiang, J. Jung, A. B. Kahng, V. N. Kravets, Y.-L. Li, S.-T. Lin and M. Woo,
"DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design",
Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020, pp. 1-6 (Invited).
(Link)
[c10]
T.-B. Chan, A. B. Kahng and M. Woo,
"Revisiting Inherent Noise Floors for Interconnect Prediction",
Proc. ACM International Workshop on System-Level Interconnect Prediction (SLIP^2), 2020, pp. 1-7.
(Link)
[c11]
D. Kim, H. Kwon, S.-Y. Lee, S. Kim, M. Woo and S. Kang,
"Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator",
Proc. Design, Automation and Test in Europe (DATE), 2021, pp. 1809-1814.
(Link)
[c12]
C. Chidambaram, A. B. Kahng, M. Kim, G. Nallapati, S.C. Song and M. Woo,
"A Novel Framework for DTCO: Fast and Automatic Routability Assessment with Machine Learning for Sub-3nm Technology Options",
Proc. IEEE Symposium on VLSI Technology, 2021, pp. 1-2.
(Link)
[c13]
C.-K. Cheng, A. B. Kahng, I. Kang, M. Kim, D. Lee, B. Lin, D. Park and M. Woo,
"CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation",
Proc. ACM/IEEE International Conference on Computer Design, 2021, pp. 366-373.
(Link)
[c14]
J. Chen, I. H.-R. Jiang, J. Jung, A. B. Kahng, S. Kim, V. N. Kravets, Y.-L. Li, R. Varadarajan and M. Woo,
"DATC RDF-2021: Design Flow and Beyond",
Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021, pp. 1-6 (Invited).
(Link)
[c15]
A. B. Kahng, S. Thumathy and M. Woo,
"An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing",
Proc. IEEE International Symposium on Quality Electronic Design (ISQED), 2023, pp. 1-8.
(Link)
[c16]
J.-W. Jeon, A. B. Kahng, J.-H. Kang, J. Kim and M. Woo,
"SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization",
Proc. IEEE International Symposium on Quality Electronic Design (ISQED), 2024, pp. 1-8
(Link)
[c17]
A. B. Kahng, B. Pramanik and M. Woo,
"A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop",
Proc. Great Lakes Symposium on VLSI (GLSVLSI), 2024, pp. 1-7
(Link)
Journal
[j1]
H. Kwon, M. Woo, S. Kang and Y. Kim,
"Statistical Leakage Analysis Using Gaussian Mixture Model",
IEEE Access 6 (2018), pp. 51939-51950.
(Link)
[j2]
M. Fogaça, A. B. Kahng, E. Monteiro, R. Reis, L. Wang and M. Woo,
"On the Superiority of Modularity-Based Clustering for Determining Placement-Relevant Clusters",
Integration: The VLSI Journal 74 (2020), pp. 32-44.
(Link)
[j3]
C.-K. Cheng, A. B. Kahng, H. Kim, Minsoo Kim, D. Lee, D. Park and M. Woo,
"PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(5) (2022), pp. 1495-1508.
(Link)
[j4]
A. B. Kahng, M. Kim, S. Kim and M. Woo,
"RosettaStone: Connecting the Past, Present and Future of Physical Design Research",
IEEE Design and Test of Computers 39(5) (2022), pp. 70-78.
(Link)
Projects
Circuit Projects
RePlAce [c3][c4][j2] - RePlAce is a global placement tool for spreading and placing standard cells by minimizing wire-length. RePlAce solves the electrostatic PDEs for density calculation, which is a core algorithm for spreading the standard cells. I've rewritten the whole RePlAce as clean C++11 code based on OpenDB, which means RePlAce now fully supports LEF/DEF commercial formats in fast. RePlAce has been verified with 7/12/14/28/45/65/130 nm technologies. Routability-driven and Timing-driven are implemented with OpenSTA and FastRoute APIs within OpenROAD. RePlAce is available as the 'global_placement' command in the OpenROAD flow.
OpenDP [c2][c3][c4] - Proposed fence-region and multi-deck-aware open-source detailed placer that utilizes the Si2 LEF/DEF parser. This project achieved 63% smaller displacement and 70% runtime reduction compared with ICCAD 2017 contest winner. OpenDP is used in Synthesis, Gate-sizing, and Clock Tree Synthesis (CTS) within the OpenROAD flow. OpenDP is available as the 'legalize_placement' command in the OpenROAD flow.
Triton Macro Place [c3][c4] - ParquetFP based macro cell placer for the OpenROAD. Generate a placed DEF with macro placements honoring halos, channels and cell row 'snapping'. Approximately ceil((#macros/3)^(3/2)) 'sets' corresponding to quadrisections of the initial placed mixed-size DEF are explored and packed using ParquetFP-based annealing. The best resulting floorplan according to a heuristic evaluation function is returned. TritonMP is available as the 'macro_placement' command in the OpenROAD flow.
RDF Calibration Testcases [c5][c9][c14] - Provides publicly-available timer, RC parasitic and static IR drop calibration testcases. This project utilized the OpenROAD flow with three open-sourced PDKs (NanGate45, SkyWater130HD/HS).
SLO-ECO [c13][c16] - SLO-ECO solves detailed placement and detailed routing simultaneously at the post routeOpt (PRO) stage, using the Z3 SMT solver. Also, SLO-ECO considers the single-line-open (SLO) violations from physical verification stage. Translated all Perl scripts into clean C++14 with OpenROAD structures.
PROBE 2.0 [j3] - Proposed a new Kth metric using knight's tour for the design-technology co-optimization (DTCO). Generates cell LEFs from a satisfiability modulo theories (SMT) solver's output. Contains AutoML H2O flow to predict Kth for auto-generated cell's routability evaluation.
Clip Graph Extractor (OpenROAD EDA Tutorial) - Extracts a sub-graph from placed and routed circuit layout with clip coordinates. This project was used as an example of adding a tool for the OpenROAD and machine learning EDA tutorial. This project registers Python modules (GraphExtractor_py) using the SWIG wrapper.
FLEX/BISON Verilog Parser for C++ - Improves the previous Ben-marshall's verilog parser to be successfully compiled under c++11/c++14 environments.
Verilog to DEF Translator - Convert hierarchical/flat gate-level Verilog to a flat DEF file. This project traverses all hierarchical modules with BFS. This project used the OpenSTA's ConcreteNetwork API.
GRASP based Metaheuristics for Layout Pattern Classification [c1] - Proposed new methodology for layout pattern calssification problem.
Web Projects
Auto SSH Local/Remote Tunneling - A bash script that detects whether a tunneling connection is broken and automatically reconnects. This script would be combined with the crontab scheduler. (Support Ubuntu/Centos)
UNIST Bus Info - Web site for Bus arrival in UNIST.